1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a multilayer interconnect structure.
2. Description of the Related Art
For manufacturing a semiconductor device including a multilayer interconnect structure formed on a semiconductor substrate, use of a low dielectric constant material, which is referred to as low-k material, has been studied, as an insulating interlayer for reducing a parasitic capacitance between interconnects. The semiconductor devices including the multilayer interconnect structure in which the low dielectric constant film is employed as the insulating interlayer are formed in a plurality of numbers on a wafer, and then split into individual devices by dicing.
At the dicing process, however, a nick is often made on a cut section. Since the nick is where a stress concentrates, a crack is prone to be created from the nick. Accordingly, when the nick is made by dicing close to an interface of stacked insulating films, the crack may propagate along the interface from the cut section to an inner portion of the semiconductor substrate.
Especially in the case where the low dielectric constant film is employed as the insulating interlayer, the propagation of the crack incurs a significant impact. For example, if the low dielectric constant film is exposed on the diced section at the wafer dicing process, the low dielectric constant film may separate from the adjacent layers under a heat cycle of a subsequent temperature cycle test and so on.
Such problem of the crack along the interface is also incidental to a semiconductor device including a circuit with a fuse, in addition to the dicing process, and therefore constitutes an important issue to be addressed.
For suppressing propagation of a crack, JP-A No. H10-172927 proposes forming a slit on a main surface of a semiconductor chip so as to surround a guard ring, in a semiconductor device including a multilayer interconnect structure in which a BPSG (Boron-doped Phosphor Silicate Glass) is employed as part of an insulating interlayer. According to this document, such structure can be considered to effectively inhibit a crack from propagating into an inner portion of the chip.
However, it has now been discovered that the technique according to the cited document requires forming a deep slit on the semiconductor substrate that penetrates a plurality of interconnect layers. Accordingly, as the number of stacks of the interconnect layer increases, the slit has be to formed in a greater aspect ratio, which makes it all the more difficult to perform the etching to form the slit. Therefore, this technique still has a room for improvement, from the viewpoint of the device configuration and simplification of the manufacturing process.